CAT34TS02
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14
Table 10. CAPABILITY REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
B7
B6
B5
B4
B3
B2
B1
B0
EVSD
TMOUT
RFU
TRES [1:0]
RANGE
ACC
EVENT
Bit
Description
B15:B8
Reserved for future use; can not be written; should be ignored; will read as 0
B7 (Note 11)
0:
Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set
(i.e. a TS shutdown freezes the EVENT
output)
1:
Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set
(i.e. a TS shutdown deasserts the EVENT
output)
B6
0:
The TS implements SMBus timeout within the range 10 to 60 ms
1:
The TS implements SMBus timeout within the range 25 to 35 ms
B5
0:
Pin A
0
V
HV
compliance required for RSWP Write/Clear operations not explicitly stated
1:
Pin A
0
V
HV
compliance required for RSWP Write/Clear operations explicitly stated
B4:B3
00:
LSB = 0.50癈 (9 bit resolution)
01:
LSB = 0.25癈 (10 bit)
10:
LSB = 0.125癈 (11 bit)
11:
LSB = 0.0625癈 (12 bit)
B2
0:
Positive Temperature Only
1:
Positive and Negative Temperature
B1
0:
?癈 over the active range and ?癈 over the operating range (Class C)
1:
?癈 over the active range and ?癈 over the monitor range (Class B)
B0
0:
Critical Temperature only
1:
Alarm and Critical Temperature
11.Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a 1 to Configuration Register
bit 5 (EVENT
output can be de-asserted during TS shut-down periods)
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